Architect / R&D Engineer / Senior R&D Engineer

Real Intent
Coral Springs, FL

THE OPPORTUNITY

If you are looking for an exciting career move, find one with a successful start up in the field of Electronic Design Automation, Real Intent is looking for new applications engineers to join its team! Come work with a team of top notch experts in the field of clock verification, RTL sign off and automatic formal. We offer an exciting work environment with competitive compensation and benefits.

Responsibilities

The FAE is a vital member of the Applications Engineering Team. The FAE works with customers to provide superb technical consultation and maintain strong customer relationships. The position has primary responsibility for the technical success of software evaluations at prospective customers as well as tool deployment in existing accounts. Candidates must be able to effectively work with Engineering and Marketing departments to define software improvements, address market opportunities, and resolve customer issues with software tools. Some travel required.

Qualifications

  • BSEE or Computer Engineering or equivalent plus 2-3 years of experience or MSEE or Computer Engineering with 1-2 years of experience in digital design, hardware verification, or applications engineering, with a proven track record for customer satisfaction
  • Detailed working knowledge of Verilog and/or VHDL; SystemVerilog familiarity required, working knowledge a plus
  • Excellent communication and technical presentation skills, both verbal and written
  • A self-starter with a history of driving projects to completion under tight schedules
  • Hands-on, technical in-depth experience in at least two of the following areas:
    • Asynchronous clock domain crossing verification on large SoC designs
    • Current commercial hardware RTL linting technologies, including detailed knowledge of rule sets
    • Hardware static timing analysis (STA) / timing closure flows
    • Assertion-based formal property hardware verification
    • Testbench-driven hardware simulation flows

To apply, email resume to: ***email_hidden***

Posted 2026-05-06

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